1. Field of the Invention
The present invention relates to a buffer circuit for buffering an incoming signal, and more particularly, to an output buffer circuit provided at the signal output portion of a semiconductor device such as a semiconductor integrated circuit device.
2. Description of the Background Art
A semiconductor device such as a semiconductor integrated circuit device includes a buffer circuit for signal waveform shaping or for driving a circuit of the succeeding stage at a high speed. One of such buffer circuits is a buffer circuit for externally providing a signal internally processed in a device (or in a functional block).
FIG. 14 schematically shows a structure of a semiconductor device which is one of conventional semiconductor integrated circuit devices. Referring to FIG. 14, a semiconductor device 500 includes an internal circuit 502 for carrying out a desired process on an input signal D, and an output buffer 504 for buffering a signal from the internal circuit 502. The output of the output buffer 504 is provided to the input portion of an external circuit 510 provided separately from the semiconductor device 500. The semiconductor device 500 may be of one semiconductor chip, or a functional block that executes one function in a semiconductor chip. The output buffer 504 drives at high speed an output signal line (the signal line between the output buffer 504 and the external circuit 510) according to a signal provided from the internal circuit 502.
FIG. 15 shows a structure of a conventional output buffer circuit. Referring to FIG. 15, an output buffer circuit 520 includes two cascade-connected inverter circuits 522 and 524. The output of the output buffer circuit 520 is supplied to the input of the external circuit 510 of FIG. 14. In general, there is impedance in the input portion of a circuit. This impedance is shown as an external load circuit 530 in FIG. 15. The external load circuit 530 includes a parasitic impedance with a capacitive load 532 and a resistive load 534 provided parallel to each other.
The output buffer circuit 520 has a great driving capability for driving the external load circuit 530 speedily and properly. The driving capability of the inverter circuit 524 is particularly of a great value.
In operation, the output buffer circuit 520 responds to an input signal VIN to charge and discharge the capacitive output load 532 included in the external load circuit 530. The signal VOUT provided from the output buffer circuit 520 varies according to a time constant determined by the capacitance and resistance of the capacitive load 532 and the resistive load 534, respectively, of the external load circuit 530.
There is a parasitic inductance 536 in addition to the parasitic capacitance (included equivalently in the capacitive load 532) in the signal line. Switching noise occurs by this parasitic inductance when the output signal VOUT from the output buffer circuit 520 changes at a high rate.
There is a change in the current in the output signal line when the logic level of the output signal VOUT from the output buffer circuit 520 changes. Voltage is induced in the parasitic inductance 536 according to this current change. The magnitude of the voltage induced by the parasitic inductance 536 is proportional to the changing rate of the current. The induced voltage by the parasitic inductance 536 is generated in a direction opposite to the voltage change of the output signal from the output buffer circuit 520. Therefore, ringing occurs in the output signal VOUT from the output buffer circuit 520 to cause overshooting and undershooting in the signal, as shown in FIG. 16. The generation of ringing such as overshooting and undershooting is time-consuming for the signal to attain its stable state, resulting in decrease in the circuit operation speed.
As an integrated circuit device is increased in speed, the changing speed of the output signal VOUT from the output buffer circuit 520 becomes greater. In this case, the induced voltage is also increased to deteriorate the circuit operation as "switching noise". Particularly, the induced voltage by the parasitic inductance 536 is transmitted to ground potential via a pull down transistor of the inverter circuit 524 included in the output buffer circuit 520. Therefore, a phenomenon called "ground bounce" (corresponding to the ringing generated at the fall of the output signal VOUT in FIG. 16) is generated whereby the ground potential of the semiconductor device 500 in FIG. 14 changes to degrade the circuit operation.
More specifically, when the output buffer 500 according to the structure shown in FIG. 14 provides a signal of a L level, there may be a case where the level of this signal will become greater than the threshold voltage of the input element in the input portion of the external circuit 510 on account of the induced voltage, resulting in an erroneous determination in the external circuit 510 that a signal of a H level is provided from the output buffer 504. Furthermore, because the threshold voltage of the input buffer (not shown) in the semiconductor device 500 of the configuration in FIG. 14 is changed by the ground bounce, a negative ground bounce will cause the threshold voltage of the input buffer of the semiconductor device 500 to be lower than the L level of the input signal D to yield a problem of erroneous operation.
When the load of the external load circuit 530 is great, the output buffer circuit 520 has a great driving capability for driving the external load circuit 530 at a high speed. In this case, the change in the output signal from the output buffer circuit 520 is abrupt. As shown in FIG. 17, there is caused a great current flow in the power supply line or ground line at the time of change in the signal. The power supply line or ground line has a relatively great parasitic inductance by the lead frame or bonding wire in a package. Therefore, a noise called "voltage spike" is generated in the power potential Vdd or ground potential Vss according to the great current change to cause ringing in the output signal VOUT from the output buffer circuit, causing a problem that erroneous operation tends to occur in the external circuit 510.
Even if the power supply current or ground current is not great, any abrupt change in current will cause a generation of noise in the power supply line and or ground line by the parasitic inductance component thereof. Because the power supply line and the ground line are connected to many circuits in the semiconductor device, the noise in the power supply line or ground line will become the cause of erroneous operation in the semiconductor device or the external device.
If the change in the output signal from the output buffer is abrupt, a similar noise will be generated even if the external load is not so great. Consider a case where the output buffer 504 includes four output buffer circuits 550, 552, 554, and 556 as shown in FIG. 18. Each of output buffer circuits 550-556 implements a CMOS inverter circuit. A power supply line and a ground line are connected in common to output buffer circuits 550-556 to provide operating power supply potential Vdd and ground potential Vss.
Consider a case where the input signal VA of the output buffer circuit 550 remains at the H level, and the remaining input signals VB, VC, and VD rise from the L level to the H level. In this state, the output of the output buffer circuit 550 attains an L level, and the outputs of the remaining output buffer circuits 552, 554 and 556 fall to the L level. When the output signal attains a L level, the charges of external load capacitors 562, 564, and 566 are discharged to the ground line. If the signal change in output buffer circuits 552, 554 and 556 is abrupt, discharge current I flows abruptly from external load capacitors 562, 564 and 556 to the ground line. This means that a great discharge current flows abruptly to the ground line to change the potential Vss of the ground line (illustrated by N in FIG. 18). The noise (voltage spike N) generated in the ground line is provided via the output buffer circuit 550 to be superimposed on the output signal VAO. Therefore, there is a possibility of the output signal VAO being erroneously determined as an H level.
In the reversed case where the input signal VA is fixed to a L level, and the remaining input signals VB, VC and VD change from the H to L level, a charging current will flow abruptly to external load capacitors 562, 564 and 566 from the power supply line supplying power supply potential Vdd to generate noise in power supply potential Vdd. This noise is provided via the output buffer circuit 550 to generate noise in the output signal VAO.
Because a buffer circuit using an inverter circuit and the like has an abrupt change in the output signal, noise or ringing will be generated in the output signal, or noise such as voltage spike will be generated in the power supply line or ground line due to an abrupt change in the charging/discharging current in driving an external load, resulting in erroneous operation. Various measures are taken to reduce such noise.
FIG. 20 shows a structure of a conventional output buffer circuit, disclosed in Japanese Patent Laying-Open No. 60-136238, for example. Referring to FIG. 20, the output buffer circuit includes inverter circuits 103 and 101 cascade-connected in two stages. The inverter circuit 100 includes a p channel MOS transistor 101 and an n channel MOS transistor 102 complementarily connected between a power supply node 1 supplying power supply potential Vdd and a ground node 2 providing ground potential Vss. Transistors 101 and 102 have their transistor sizes increased for driving external load, and has a great current driving capability. The output buffer further includes a capacitor 104 provided between the output portion of the inverter circuit 103 and the input portion of the inverter circuit 100. The capacitor 104 has one electrode connected to the node 103a and the other electrode connected to the ground node 2 supplying ground potential Vss. The operation thereof will be described hereinafter with reference to FIG. 21 which is an operational waveform diagram thereof.
When the input signal applied to the input node 3 rises from the L level to the H level, the output of the inverter circuit 103 falls from the H level to the L level. This change in the output level of the inverter circuit 103 is equivalent to discharging of the charges in the capacitor 104. Therefore, the potential in the node 103a falls slowly. When the potential level of the node 103a becomes lower than the threshold voltage 101a of the p channel MOS transistor 101 included in the inverter circuit 100, the p channel MOS transistor 101 conducts, whereby a charging current from the power supply node 1 begins to flow to the output node 4. In response to the decrease of potential in the node 103a, the transistor 101 makes gradual transition towards the on state and the transistor 102 is gradually brought to the off state, whereby the potential of the output node rises slowly. By decreasing the potential rising speed of the output node 4, current can be prevented from flowing abruptly from the power supply node 1 to suppress the generation of abrupt current change in the power supply line to prevent noise generation. When the potential of the node 103a reaches the L level of the ground potential Vss level, transistors 101 and 102 are turned on and off, respectively, whereby the potential of the output node 4 is maintained at the power supply potential Vdd level of H.
When the signal provided to the input node 3 falls from the H to L level, the output of the inverter circuit 103 rises from the L to H level. The rising speed of the output of the inverter circuit 103 is rate-determined by the charging speed of the capacitor 104. Therefore, the rise of the input signal of the inverter circuit 100 is decreased in speed. When the potential of the node 103a becomes greater than the threshold voltage 102a of the n channel MOS transistor 102, the n channel MOS transistor 102 conducts, so that the output node 4 is discharged to ground potential Vss2. Therefore, the potential of the output node 4 begins to fall slowly.
When the node 103a eventually reaches the power supply potential Vdd level of H, transistors 101 and 102 are turned off and on, respectively, whereby the output node 4 is maintained at the ground potential Vss level of L. By mitigating the signal change in driving the output node 4 to a L level, the changing speed of current flowing into the ground node 2 can be lowered to decrease the current changing speed of the ground line to reduce noise generation.
In other words, the generation of ringing in the signal in the power supply line, the ground line, or the output signal line or noise such as a voltage spike can be prevented by decreasing the changing speed of current flowing into the power supply line or the ground line.
Why the potential changing speed of the output node 4 depends upon the potential changing speed of the node 103a is that the current amount supplied from a MOS transistor is determined by the gate voltage. (In saturated operation, the drain current Id is proportional to the square of the gate voltage Vg.)
In the output buffer circuit of FIG. 20, the input node 103a of the inverter circuit 100 provided at the output stage has the potential changing speed decreased. Therefore, the time period of the gate voltage of an intermediate value is increased in the p channel MOS transistor 101 and the n channel MOS transistor 102. Therefore, the time when both transistors 101 and 102 simultaneously attain a conductive state is increased, whereby a through-current flows from the power supply node 1 to the ground node 2, resulting in increased wasteful consumed current.
The time point of the inverter circuit 101 of the output stage initiating its operation is when the potential of the node 103a becomes lower than the threshold voltage 101a of the p channel MOS transistor 101 or higher than the threshold voltage 102a of the n channel MOS transistor 102. Therefore, for initiation in the potential change of the output node 4, delay times of D1 and D2 are respectively required from the time point of change in the signal applied to the input node 3. This means that the delay in the output buffer circuit is increased to degrade the high speed response characteristics (delay characteristics), resulting in lowering of the high speed operation performance of the overall device.
An output buffer circuit such as one shown in FIG. 22 is proposed to solve such problems of through-current and response characteristics.
FIG. 22 is a modification of a conventional output buffer circuit, and is disclosed in, for example, Japanese Patent Laying-Open No. 61-260719. The output buffer circuit of FIG. 22 includes a buffer circuit 201 having a relatively small driving capability and responsive to a signal applied to the input node 3 for driving the output node 4, a three-state buffer circuit 202 having a relatively high driving capability and a high impedance output state, responsive to a signal on the input node 3 for driving the output node 4, and a control circuit 203 for controlling the operation of the buffer circuit 202 according to the signal potentials of the input node 3 and the output node 4.
The control circuit 203 includes a match detection circuit 211 for receiving the signal on the input node 3 and the signal on the output node 4, and an inverter circuit 212 for receiving the output of the match detection circuit 211. The output of the inverter circuit 212 is supplied to the control terminal of the three-state buffer circuit 202. The buffer circuit 20 is made of small transistors which gives it relative small driving capability. The three-state buffer circuit 202 is made of large transistors which gives it great driving capability. The operation thereof will be described with reference to FIG. 23 which is an operation waveform diagram thereof.
When the potential of the signal supplied to the input node 3 rises to a H level, the buffer circuit 201 raises the potential of its output node. Because the driving capability of the buffer circuit 201 is small, the potential of the output node 4 rises slowly. Because the potential of the output node 4 has not yet thoroughly reached an H level when the potential of the input node 3 attains a H level, the match detection circuit 211 in the control circuit 203 will have different potential logic values in the inputs to provide a signal of a L level, whereby the potential of the signal provided from the inverter circuit 212 to the node 205 rises to a H level. Therefore, the three-state buffer circuit 202 enters a high impedance output state.
When the potential of the output node 4 reaches a certain potential, the potential levels of the input node 3 and the output node 4 will match to result in an output of a H level from the match detection circuit 211, whereby the signal provided from the inverter circuit 212 to the node 205 attains an L level. Therefore, the three-state buffer circuit 202 becomes active to drive the output node 4 to a H level by its great driving capability. Then, the output node 4 is driven by the three-state buffer circuit 202 having a great driving capability, whereby the potential level is stabilized led at the H level.
In the case where the signal provided to the input node 3 falls to a L level from the H level, the output of the match detection circuit 211 becomes L in response to the decrease in potential of the input node 3, which in turn causes the output of the node 205 to attain a H level. As a result, the three-state buffer circuit 202 attains a high impedance output state, so that the output node 4 is driven by the buffer circuit 201 of a small driving capability to have its potential level falling slowly. When the potential of the output node 4 falls to a predetermined level, the output of the match detection circuit 211 and then the potential level of the node 205 attain the L level. Therefore, the three-state buffer circuit 202 is activated, whereby the output node 4 is driven at a high speed to a L level. In this state, the output node 4 is held stably at the L level by the buffer circuit 202 of a high driving capability.
In summary, according to the configuration of the buffer circuit of FIG. 22, the output node 4 is driven by the buffer circuit 201 in response to a signal applied to the input node 3 to decrease the speed of the potential change in the output node 4, and the output node 4 is driven by a buffer circuit 202 of a great driving capability when the potential of the output node 4 approaches a target value so that the driving capability under a stable state is increased to stabilize the signal potential of the output node 4.
Because the output node 4 is driven by the buffer circuit 201 in response to a signal applied to the input node 3 in the buffer circuit of FIG. 22, the problem of delay in the signal response characteristics is solved. Furthermore, the matter of reducing the current consumption is also achieved because the through-current flows only for a short time period even if buffer circuits 201 and 202 are implemented with a CMOS transistor, by virtue of the input signal change at the input node 3 being directly provided to buffer circuits 201 and 202.
However, the buffer circuit of FIG. 22 is increased in circuit size because two buffer circuits of a buffer circuit 201 and a three-state buffer circuit 202 are required. In a semiconductor integrated circuit, the occupying area of such buffer circuit will become great, to provide a great bottleneck against increasing the integration density.
When the potential changing speed of the output node 4 is to be decreased, the potential changing speed is determined uniquely by the driving capability of the buffer circuit 201. The driving capability of the buffer circuit 201 is determined by the size of the transistor which is a circuit component. The current supplying capability particularly depends upon the gate width W when a MOS transistor (insulated gate type field effect transistor) is used. Therefore, there is a problem that it is difficult to set the potential changing rate in the output node 4 to a desired value. Also, the discharging/charging current of a MOS transistor depends upon the drain current IDS which is proportional to the ratio of the gate width W to the gate length L, i.e. to W/L. Once the transistor size is determined, it is difficult to modify the size after manufacturing, causing a problem that a desired current/potential changing speed can not be easily obtained.